Lattice announces ispLEVER 5.0 programmable logic design tool suite

From: Lattice Semiconductor
Published: Fri May 06 2005

Lattice Semiconductor Corporation (NASDAQ: LSCC) has announced the immediate availability of its ispLEVER 5.0 programmable logic design tool suite. Major additions and improvements to design flow and documentation make the ispLEVER features and point tools easy to learn and easy to use. Exceptional performance continues to be a hallmark of ispLEVER software, with design frequency, logic utilization and compilation time all substantially improved.

Lattice ispLEVER 5.0 includes support for the new LatticeXP non-volatile, infinitely reconfigurable FPGAs. Lattice ispLEVER 5.0 provides instant access not only to the latest ispXP technology, but also to all Lattice FPGA, FPSC, CPLD and SPLD programmable devices. The ispLEVER tool suite is available in Windows, UNIX and LINUX versions.

"Our customers can unleash the power of Lattice programmable logic devices effectively and efficiently with a design system that is extraordinarily user friendly, offers exceptional functionality and performance and is now value priced at $695," said Stan Kopec, Lattice vice president of corporate marketing.

Lattice vice president of software Chris Fanning said, "We’ve made ispLEVER 5.0 easier to learn and use than ever before, while adding many new and enhanced features and point tools. At the same time, our logic optimization engine has been enhanced to give unprecedented performance and quality of results."

Best of breed synthesis and simulation
The ispLEVER 5.0 tool suite includes Synplicity’s Synplify software for Lattice 8.0 synthesis. This latest version of Synplify improves both speed and quality of results. "Close collaboration over years of partnership with Lattice has now raised the bar for FPGA performance," said Andy Haines, vice president of marketing for Synplicity. "The formidable combination of Synplify and ispLEVER software with the new Lattice FPGA silicon sets a new performance benchmark for the industry. We’re excited about our recently expanded OEM agreement with Lattice, and look forward to delivering exceptional performance to our mutual customers for many years to come."

The ispLEVER 5.0 release marks the full integration and shipment of the Mentor Graphics Precision RTL synthesis and ModelSim simulation tools with the Lattice design tool suite. "This development is especially important for FPGA designers because it is the first time that commercial, advanced versions of synthesis and simulation tools for complex FPGA design have been offered via any OEM offering to date," said Simon Bloch, General Manager, Design Creation and Synthesis Division, Mentor Graphics. "Through our agreement with Lattice, we have opened up the full breadth of Mentor’s superior FPGA design flows and capabilities to our mutual customers, resulting in improved overall productivity and significantly lower silicon costs."

Ease of use, ease of learning emphasized
Significant additions and enhancements to documentation and tutorials make learning and mastering the ispLEVER design environment easier than ever. Special emphasis has been placed on providing tutorials and examples throughout ispLEVER’s design flow and point tools. Learning resources have been comprehensively updated and integrated, including a new, faster help system with links to datasheets and resources on Lattice’s website,

Robust functionality
Top-level schematic design has been added to ispLEVER 5.0, which allows the user to create design function blocks and quickly visualize the entire design in a graphical representation. This not only helps partition the design into manageable elements, but also simplifies the design review process. Every point tool in ispLEVER 5.0 also has been enhanced. The Module/IP Manager GUIs have been streamlined for better ease of use, and many new IP modules have been added for customers’ designs. Over 20 new DSP elements have been added to the ispLEVER DSP design library; the I/O Assistant, which facilitates complex I/O assignment and rule checking, has been upgraded; significant enhancements have been made to the Floorplanner to provide additional functionality, including multiple windows; the accuracy and flexibility of the Power Calculator have been enhanced; and the ispTRACY Logic Analyzer provides new cross-referencing, core integration facilities and optimized displays. A complete list of new ispLEVER 5.0 features and enhancements can be viewed at

New product packaging and starter system upgrade
The ispLEVER 5.0 release marks a major advancement in the way ispLEVER tools are configured and licensed. All customers now have access to design tools for all Lattice products, providing unmatched value to the user. The downloadable ispLEVER-Starter configuration has also been expanded to include support for the entire LatticeEC FPGA family as well as added support for LatticeECP-DSP devices.

Availability and pricing
The ispLEVER 5.0 HDL-BASE design tools for Windows, now supporting all Lattice programmable logic families and including ModelSim LE, Precision RTL Lattice Edition and Synplify 8.0, is list priced at $695 and is available immediately. UNIX and LINUX versions are also available.

# # #

About Lattice Semiconductor
Lattice Semiconductor Corporation provides the industry’s broadest range of Field Programmable Gate Arrays (FPGA) and Programmable Logic Devices (PLD), including Field Programmable System Chips (FPSC), Complex Programmable Logic Devices (CPLD), Programmable Mixed-Signal Products (ispPAC) and Programmable Digital Interconnect Devices (ispGDX). Lattice also offers industry leading SERDES products.

Lattice is "Bringing the Best Together" with comprehensive solutions for system design, including an unequalled portfolio of non-volatile programmable devices that deliver instant-on operation, security and "single chip solution" space savings.

Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in communications, computing, industrial, consumer, automotive, medical and military end markets. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124-6421, USA; telephone 503-268-8000, fax 503-268-8037. For more information about Lattice Semiconductor Corporation, visit

Statements in this news release looking forward in time are made pursuant to the safe harbor provisions of the Private Securities Litigation Reform Act of 1995. Investors are cautioned that forward-looking statements involve risks and uncertainties including market acceptance and demand for our new products, our dependencies on our silicon wafer suppliers, the impact of competitive products and pricing, technological and product development risks and other risk factors detailed in the Company’s Securities and Exchange Commission filings. Actual results may differ materially from forward-looking statements.

Lattice Semiconductor Corporation, Lattice (& design), L (& design), ispLEVER, ispLeverDSP, LatticeECP-DSP, LatticeEC, LatticeXP, ispTRACY, ispXP, ispGDX, ispPAC and specific product designations are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries.

GENERAL NOTICE: Product names used in this publication are for identification purposes only and may be trademarks of their respective holders.

Company: Lattice Semiconductor
Contact Name: Bernie Perrin
Contact Email:
Contact Phone: +44 (0)1932 825741

Visit website »